The invention relates to an integrated circuit having a semiconductor arrangement. Such an integrated semiconductor arrangement can be, for example, as a power transistor, a DMOS, HVMOS, MedV-MOS, LowV-MOS or bipolar transistor which, together with other components, is provided in a semiconductor body.
It has been found that in such integrated semiconductor arrangements, if, for example, an N-DMOS transistor with an n-type conducting drain zone is operated in a low-side application, the potential of this drain zone can be pulled, by a short circuit or by an inductive load, to a value which is less than 0 V compared with a p-type conducting insulation region. In this mode, the drain substrate diode is polarized in the forward direction and very large currents up to several amperes can flow into the substrate. In the case of N-DMOS transistors, electrons are minority charge carriers in the substrate.
In this respect, reference is made to the attached FIG. 1 in which, in a section drawn on the left and designated by I of a semiconductor body, on or in a p-type substrate 1 in a first semiconductor well 4a, an N-DMOS transistor is located which is here illustrated diagrammatically by its n+-type doped drain zone 9 extending up to the top main area H and which carries a negative injection potential Vinj<0 V injecting a reverse current. Furthermore, in a second section of the semiconductor body illustrated in FIG. 1, drawn on the right and designated by II, in a second n-type semiconductor well 4b semiconductor zones 6, 7 of different conduction type, e.g., semiconductor zones of a PMOS and of an NMOS transistor are formed from the main area H. The semiconductor zones 6 of the PMOS transistor are located in an n-type doped semiconductor well 5a and the semiconductor zones 7 of the NMOS transistor are formed in an adjoining p-type semiconductor well 5b, both of which are formed next to one another in the aforementioned second semiconductor well 4b. Between the p-type substrate 1 and the first semiconductor well 4a, on the one hand, and the p-type substrate 1 and the second semiconductor well 4b, on the other hand, n+-type doped buried layers 2a and 2b are in each case located. The buried layer 2a is connected to the drain electrode 9 of the N-DMOS transistor in the depth of the first semiconductor well 4a whereas the buried layer 2b is connected to a particular well potential Vn-well via an n+-type sinker 3. Furthermore, a respective gate potential VG is applied to the gate terminals of in each case the PMOS transistor and of the NMOS transistor in the second semiconductor well 4b in FIG. 1.
The negative charge carriers injected from the drain zone 9 pulled to under the p-type substrate potential in the case described are illustrated with arrows designated by the symbol e− in FIG. 1. These injected charge carriers flow from the drain zone 9 via the substrate into the n+-type sinker 3 and can lead to a malfunction or to the destruction of the chip. This problem or malfunction can not always be solved with a p+-type insulation indicated with the reference number 8 in FIG. 1.
FIG. 2 illustrates a guard ring design hitherto used, which in comparison with the semiconductor arrangement of FIG. 1, is formed by an additional second p+-type insulation 8b. The electrons e− injected from the drain zone 9 of an adjacent N-DMOS transistor are marked by arrows. The pattern, illustrated in FIG. 2, with the two active guard rings 8a, 8b extending into the p-type substrate 1 is efficient without trench insulation because more than 80% of the electrons injected into the substrate is injected into the p+-type insulation 8a, 8b on the surface. Fewer electrons are injected via the buried layer 2b because the connection of the n+-type sinker 3 with the buried layer 2b is some ohms. The greatest voltage drop thus exists between the injecting n-type well 4a and the p-type substrate 1 on the surface. The regions 9, 8 and 3 form a bipolar transistor which turns itself off, 9 forming its emitter, 8 forming its base and 3 forming its collector. Base 8 and collector 3 are short circuited in this arrangement.
If trenches were then used for insulating the injecting components, i.e. of the drain zone 9, indicated on the left in FIG. 2, of the N-DMOS power transistor, the electrons e− would be injected into the substrate essentially via the buried layer 2a. However, the active guarding pattern according to FIG. 2 could then no longer be constructed. Surface guard rings cannot absorb the injected electrons.
For these and other reasons, there is a need for the present invention.